The present invention generally relates to the field of information storage devices. More particularly, the present invention relates to an error detection system and method for the information storage device.
Resistive cross point memory cell arrays include memory cells which store or generate information by affecting a magnitude of a nominal resistance of the memory cells. The memory cells can include polymer elements, magnetic spin dependent tunneling (SDT) junctions or pseudo spin valve (PSV) junctions. The memory cells can also include polysilicon resistors as part of a read-only memory, or floating gate transistors as part of an optical memory, imaging device or floating gate memory device.
A resistive cross point memory cell array that includes magnetic memory cells is referred to as a magnetic random access memory (MRAM). Word lines extend along rows of the magnetic memory cells, and bit lines extend along columns of the magnetic memory cells. Each magnetic memory cell is located at an intersection of a word line and a bit line and typically includes a layer of magnetic film in which the magnetization of the magnetic film is alterable and a layer of magnetic film in which the magnetization is fixed or xe2x80x9cpinnedxe2x80x9d in a particular direction. The magnetic film having alterable magnetization is typically referred to as a data storage layer, and the magnetic film which is pinned is typically referred to as a reference layer.
A magnetic memory cell is usually written to a desired logic state by applying external magnetic fields that rotate the orientation of magnetization in its data storage layer. The logic state of a magnetic memory cell is indicated by its resistance which depends on the relative orientations of magnetization in its data storage and reference layers. The magnetization orientation of the magnetic memory cell assumes one of two stable orientations at any given time. These two stable orientations are referred to as xe2x80x9cparallelxe2x80x9d and xe2x80x9canti-parallelxe2x80x9d orientations. With parallel orientation, the orientation of magnetization in the data storage layer is substantially parallel to the magnetization in the reference layer along the easy axis and the magnetic memory cell is in a low resistance state which can be represented by the value R. With anti-parallel orientation, the orientation of magnetization in the data storage layer is substantially anti-parallel to the magnetization in the reference layer along the easy axis and the magnetic memory cell is in a high resistance state which can be represented by the value R+xcex94R. A sense amplifier can be used to sense the resistance state of a selected magnetic memory cell to determine the logic value stored in the memory cell.
Sensing the resistance state of selected magnetic memory cells can be unreliable. Manufacturing variations in the dimensions or shapes or in the thicknesses or crystalline anisotropy of the data storage layers of the magnetic memory cells can cause variations across a wafer in the memory cell R and R+xcex94R resistance values, resulting in erroneous memory cell reads.
In one approach, two memory cells are used to improve the reliability of sensing the stored logic state. With this approach, one memory cell stores a desired logic state and the other memory cell stores the opposite logic state. The resistance state is sensed by differentially comparing the resistance of the two memory cells. While this approach can improve sensing reliability and reduce the probability of read errors occurring, sensing the memory cell R and R+xcex94R resistance values can still be unreliable because the manufacturing variations do not always affect the resistance values in predictable ways.
One aspect of the present invention provides an information storage device which includes first and second memory cells which store complementary first and second logic states. An error detection system coupled to the first and second memory cells is configured to indicate an error if a difference between a first current flowing through the first memory cell and a second current flowing through the second memory cell is less than a predefined value.